Senior Principal DFT Engineer

About the role

NXP is looking for a Senior Principal DFT Engineer to lead the DFT function for its Pune MCU team. The role covers DFT architecture, instrument insertion and simulation, and works closely with the SOC lead, IP designers, DV team and BE lead.

Key responsibilities

• Architect DFT design, including DFT instruments insertion and simulation
• Work with SOC lead, IP designers and DV team to deliver DFT implementations, verify and review verification coverage
• Work with the BE lead on DFT modes such as STA and IR drop analysis
• Work with test engineers to bring up test patterns on silicon
• Provide guidance to junior DFT engineers
• Define and implement DFT structure, design and methodologies including scan, MBIST/JTAG and functional testing
• Create test vectors or oversee their creation
• Collaborate with the physical design team to close timing in DFT mode and sign off that DFT requirements are met

Required profile

• BE/MS degree in Electronics, Electrical or Computer Engineering
• 12+ years of DFT experience
• DFT lead experience for complex SOC TO and production

Required skills

• Hands-on expertise with Mentor/Synopsys test generation tools for large complex designs
• Strong fundamentals of JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, scan compression, IEEE 1500, MBIST, LBIST and SSN
• Preferred: synthesis, STA and back-end implementation flows, Tessent shell flow, lab and test-floor bring-up and debug, yield estimation and test optimization, DFT AI mindset