Principle DFT Engineer (SoC)
nxp · Bangalore
Job description
About the role
NXP is looking for an experienced DFT Engineer (7-12 years) in Bangalore to work on complex SoC designs. The role focuses on implementing and verifying scan architectures, performing scan insertion, and running gate-level simulation to validate DFT.
Key responsibilities
- Implement and verify scan architectures and perform scan insertion
- Generate and analyze ATPG patterns for stuck-at and transition faults
- Run gate-level simulation with and without SDF for DFT validation
- Collaborate with RTL, physical design and test teams to achieve high fault coverage, clean DFT signoff and timely tape-out support
Required profile
- 7-12 years of experience
- Prior experience supporting pre- and post-silicon activities is a plus
Required skills
- Hands-on expertise in Scan Insertion, ATPG and Gate-Level Simulation (GLS)
- Proficiency with Mentor/Siemens Tessent, Synopsys or Cadence DFT tools
- Solid Verilog/SystemVerilog skills
- Ability to debug DFT and GLS issues independently
Questions fréquentes
Why are you reporting this job?
Explore further
Salaries, guides and searches in India.
Salaries by job title
Apply in 30 seconds
Enter your email to apply. An account will be created automatically.
By continuing, you accept our terms of use.
Already have an account? Login
A question about this job?
Ask it here: you will get the full job summary by e-mail, right away.
Published 2 days ago
Expires 1 month from now
11 views · 0 interested
Boost your chances
Upload your CV — we will match you with relevant openings.
Analyzing your CV...
nxp
Bangalore