Principle DFT Engineer (SoC)
nxp · Bangalore
Job description
About the role
NXP is looking for an experienced DFT Engineer (7-12 years) in Bangalore to work on complex SoC designs. The role focuses on implementing and verifying scan architectures, performing scan insertion, and running gate-level simulation to validate DFT.
Key responsibilities
- Implement and verify scan architectures and perform scan insertion
- Generate and analyze ATPG patterns for stuck-at and transition faults
- Run gate-level simulation with and without SDF for DFT validation
- Collaborate with RTL, physical design and test teams to achieve high fault coverage, clean DFT signoff and timely tape-out support
Required profile
- 7-12 years of experience
- Prior experience supporting pre- and post-silicon activities is a plus
Required skills
- Hands-on expertise in Scan Insertion, ATPG and Gate-Level Simulation (GLS)
- Proficiency with Mentor/Siemens Tessent, Synopsys or Cadence DFT tools
- Solid Verilog/SystemVerilog skills
- Ability to debug DFT and GLS issues independently
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Published 1 day ago
Expires 1 month from now
8 views · 0 interested
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nxp
Bangalore