Principal Engineer - SoC Design Verification

About the role

NXP is looking for a highly experienced Design Verification (DV) engineer with 10+ years of expertise to lead verification strategy and execution for complex SoCs in Pune. The role is hands-on and requires strong technical skills, leadership and collaboration in a fast-paced environment. It suits someone with deep knowledge of ARM-based microcontrollers, low-power design verification and multiple interfaces and security IPs.

Key responsibilities

• Define and own SoC-level and IP-level verification strategy, methodology and coverage goals.
• Execute the verification plan according to product specifications and requirements defined by product architects.
• Develop, debug and run UVM-based verification environments for RTL and netlist simulation.
• Create test cases, stimulus and assertions, run regression and analyse code and functional coverage.
• Drive DV closure on diverse IPs and subsystems, ensuring maximum coverage and quality.
• Guide the team in improving flows for reuse and efficiency, mentor team members and collaborate with design teams on issues and sign-off.
• Ensure compliance with functional safety and security requirements.

Required profile

• 10+ years in SoC/IP verification with successful tape-outs of multiple SoCs.
• Bachelor's or Master's degree in Microelectronics, Electronics or Electrical Engineering.
• Comfortable working in a fast-paced environment and strong communication skills.

Required skills

• Strong expertise in ARM-based microcontrollers and SoC-level verification.
• SystemVerilog, UVM and constrained-random verification.
• Familiarity with Synopsys VCS, Cadence Xcelium and Mentor Questa.
• Low-power verification (UPF), gate-level and power-aware simulations.
• Assertions (SVA) and functional coverage.
• Interfaces such as SPI, I2C, UART, USB, PCIe, Ethernet and eSPI.
• Knowledge of Flash memory and security IPs is a plus; familiarity with analog IPs (ADC, DAC, PLLs) is also a plus.