Senior ASIC Design Engineer

About the role

NXP is looking for a Senior ASIC Design Engineer in Pune to work on wireless MAC controllers and system-level development for wireless products. The team focuses on design and verification to support new customer-requested features and new standard specifications, with emphasis on high performance, small area and low power.

Key responsibilities

• Work through the full ASIC design cycle, from micro-architecture design, RTL coding and verification, synthesis, FPGA prototyping to silicon bring-up.
• Perform IP/SoC verification in C/C++, SystemVerilog and UVM.
• Support IP delivery, FPGA prototyping and silicon validation.
• Solve complex design and verification problems with innovative approaches.

Required profile

• MSc or MSEE with 3+ years of experience.
• Working knowledge of Bluetooth, IEEE 802.15.4, wireless or other networking controller design and implementation.
• Experience in small-area and low-power design, SOC integration, and complete product cycles from specification to production.
• Hands-on FPGA validation and post-silicon bring-up experience.
• Excellent communication and reporting skills.

Required skills

• Micro-architecture, Verilog RTL coding and IP/SoC verification.
• Familiarity with ASIC design flow: HW/SW co-simulation, synthesis, lint/CDC and formal verification.
• Fluent C/C++, SystemVerilog and UVM.
• SVA assertions and coverage-driven verification.
• Perl, Python, shell scripts and Tcl.