Principal HW DFT Engineer

About the role

NXP is looking for a Principal HW DFT Engineer in Pune to architect, implement and validate in-vehicle networking devices as part of its automotive-grade products. The role covers advanced test strategies, verification and validation of pre- and post-tapeout DFT features, test coverage improvements, and close collaboration with RTL and physical teams on DFT timing constraints.

Key responsibilities

• Define and implement advanced DFT strategies, including scan architecture, JTAG, Memory BIST (MBIST) and Logic BIST (LBIST)
• Lead integration of digital subsystems, perform scan insertion and generate ATPG patterns to achieve high fault coverage
• Drive post-silicon validation and debug to root cause failures and improve manufacturing test efficiency
• Work with physical design and test engineering teams to ensure timing closure and that test patterns are ready when silicon arrives

Required profile

• B.S./M.S. in Electrical or Computer Engineering (or similar)
• 10+ years of industry experience in SoC DFT implementation, verification, static timing closure, test coverage analysis and silicon bring-up on ATE

Required skills

• EDA tool expertise: Mentor Graphics/Siemens (Tessent), Cadence or Synopsys
• DFT: scan insertion, ATPG, MBIST/LBIST, boundary scan/JTAG, test compression
• HDL: Verilog or SystemVerilog for inserting test logic and writing test wrappers
• Timing: Static Timing Analysis and DFT-specific SDC constraints
• Simulation and post-silicon debug using ATE data
• Scripting and automation with Tcl, Python or Perl