Principal Design Verification Engineer - Wireless ASIC

About the role

NXP is hiring a Principal Design Verification Engineer in Pune, India, to work on the development of wireless communication ASICs. The role sits at the centre of the organisation and influences many cross-functional teams.

Key responsibilities

• Maintain and develop the SystemVerilog/UVM test bench methodology within digital IP blocks, including circuit calibration, DSP and CPU subsystems.
• Create constrained random stimulus, write checkers and assertions, analyse simulation results and debug root causes.
• Verify power intent using methods such as UPF.
• Develop scripts to improve task efficiency and work with the digital IP design team to define comprehensive test strategies for use cases.
• Use agentic AI tools to reduce turnaround time, improve design quality and enable intelligent automation across the silicon development lifecycle.

Required profile

• BSEE or equivalent; MSEE is a plus.
• 5+ years of hardware engineering experience.
• Proven experience with verification methodologies and EDA tools such as digital simulators, waveform viewers, build/run automation and gate-level simulation.
• Good communication skills, a can-do attitude and the ability to act independently on problem solving.

Required skills

• Strong working knowledge of SystemVerilog for test bench development.
• UVM experience to build scalable, portable test benches.
• Deep knowledge of one scripting language: Python, Perl or Tcl.
• Strongly desired: C/C++ knowledge, formal and assertion-based verification, in-depth knowledge of digital logic, micro-processor and DFT architecture, and experience with communication chips.