Lead DSP Engineer - Automotive Ethernet PHY

About the role

NXP is looking for a Lead DSP Engineer to join its Automotive Ethernet PHY development team in Bangalore. You will work closely with the DSP Architect to implement and optimize DSP algorithms and architecture for next-generation automotive-grade Ethernet PHY products, collaborating with System Architecture, DFT, Verification, Validation, IC Integration and Backend teams. The role covers DSP design implementation, RTL-level integration, performance validation and timing closure support.

Key responsibilities

• Implement DSP algorithms and architecture for Automotive Ethernet PHY (e.g. 100/1000BASE-T1 and multi-gig PHYs), translating system specifications into optimized DSP RTL
• Develop synthesizable RTL for datapaths, filters, equalizers, echo cancellation, FFE/DFE, AGC and timing recovery, optimizing area, timing and power
• Create and maintain design documentation, micro-architecture specs and implementation notes
• Support the Verification team on test plans, debug and coverage closure, and the Validation team on post-silicon bring-up and performance tuning
• Contribute to model correlation between MATLAB/C-model and RTL, and run simulations and performance analyses
• Work with System Architects, DFT Architects and IC integrators, and support Backend teams on timing analysis and closure
• Maintain MATLAB/Python models, contribute to tool-flow improvements and support timing closure

Required profile

• Bachelor's or Master's degree in Electrical Engineering, Electronics, Communication Engineering or a related field
• 7+ years of experience in DSP design for communication systems
• Hands-on experience with PHY subsystems such as filtering, equalization, echo cancellation, PLLs, timing recovery and noise mitigation
• Experience supporting verification and post-silicon debug
• Preferred: automotive Ethernet PHY experience, EMC/EMI knowledge, DFT/ATPG familiarity, backend exposure, formal verification and UVM

Required skills

• Proficiency in MATLAB, Simulink, Python or C/C++ for algorithm modeling
• Strong RTL design skills (Verilog/SystemVerilog)
• Familiarity with synthesis, linting, CDC and STA flows
• Strong analytical, communication and documentation skills, able to work in cross-functional global teams