ASIC Implementation Engineer

About the role

Meta is building custom silicon to power the next generation of AI, augmented reality and virtual reality infrastructure at scale. As an ASIC Implementation Engineer on the Infrastructure Silicon team you will drive the physical implementation of complex ASICs from RTL through tape‑out, collaborating with design, architecture and verification teams.

Key responsibilities

• Run logic and physical synthesis using advanced optimization techniques and produce gate‑level netlists optimized for timing, area and power.
• Debug timing, area and congestion issues and work with RTL and physical designers to resolve them.
• Perform power estimation at RTL and gate level and identify reduction opportunities.
• Execute formal verification checks between RTL and gate‑level netlists and resolve failures.
• Run RTL lint, manage waivers and conduct DFT analysis to improve stuck‑at fault coverage.
• Develop timing constraints for synthesis and PrimeTime‑STA for blocks and top‑level designs.
• Create automation scripts and methodologies for front‑end tools (Lint, CDC, RDC, Synthesis, STA, Power).
• Collaborate with design, DV, emulation and physical design engineers to provide timing and congestion feedback.

Required profile

• Minimum 2 + years of experience as a Front‑End Synthesis & Integration Engineer.
• Hands‑on experience with RTL synthesis, design optimization for power, performance and area.
• Familiarity with front‑end and back‑end ASIC tool flows.
• Experience using SystemVerilog or other HDLs.
• Proven ability to manage multiple design releases and work cross‑functionally.

Required skills

• RTL synthesis (Design Compiler) and optimization.
• SystemVerilog HDL.
• Python and TCL scripting.
• PrimeTime STA, Spyglass, Formality (or equivalent) tools.
• Formal verification, power estimation, DFT analysis.
• Automation of front‑end EDA flows.