ASIC Design Engineer – SoC Development

About the role

Axiado is seeking an experienced ASIC/SoC Design Engineer to join its Bengaluru team. You will work across the full SoC design flow, collaborating with architecture, verification, physical design and software groups to deliver secure AI‑enabled silicon.

Key responsibilities

• Develop micro‑architecture, write RTL in Verilog, synthesize and close timing for various blocks.
• Optimize performance, bandwidth and power at top‑level and block level.
• Prototype early designs with FPGA engineers and support test program development.
• Collaborate with firmware, DV, FPGA, DFT, integration and backend teams throughout ASIC development.

Required profile

• 8+ years of experience in RTL logic design, verification, synthesis and timing optimization.
• Proven track record of at least one tape‑out and experience with FPGA bring‑up/debug on platforms such as HAPS or Veloce.
• Strong ability to write clear micro‑architecture specifications and efficient Verilog code.

Required skills

• Verilog RTL coding, synthesis, timing closure, assertions and coverage analysis.
• Interface protocol expertise: PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART.
• Scripting in Python and Perl.
• Experience with repository tools (Bitbucket, Jenkins) and issue tracking (JIRA).