Staff Analog/Mixed-Signal Design Engineer

About the role

Join Synopsys' global LPDDR PHY IP team to lead the design of high‑performance mixed‑signal IP. You will manage a group of design engineers and collaborate with architecture, verification, physical implementation, and firmware teams to deliver market‑leading DDR PHY solutions.

Key responsibilities

• Lead a team of analog and mixed‑signal design engineers through all phases of DDR PHY IP development, from specification to productization.
• Coordinate with cross‑functional groups (architect, verification, physical implementation, firmware) to ensure seamless integration.
• Drive timing, performance, and power optimization to meet stringent product goals.
• Provide technical support to customers integrating the PHY IP into their SoCs.
• Mentor and develop team members, fostering a high‑performing engineering culture.

Required profile

• BS in Electrical Engineering with 12‑15 years of experience in complex technical development.
• At least 2 years of people‑management experience.
• Strong communication skills and self‑motivation.
• Understanding of memory and memory PHY architecture is a plus.

Required skills

• Proficiency in synthesizable Verilog and SystemVerilog.
• Experience with front‑end design flows: linting, synthesis, static timing analysis (STA), cross‑domain clocking, DFT, and power‑optimization techniques.