Sr. Lead ASIC Design Engineer - Digital Design

About the role

NXP is hiring a Senior Lead ASIC design engineer for digital design in Hyderabad. The role focuses on defining and implementing hardware architectures optimized for AI inference SoCs, working across architecture, RTL, physical design and verification.

Key responsibilities

• Define and implement hardware architectures optimized for AI inference SoCs.
• Contribute to micro-architecture definition and evaluate design trade-offs for complex SoCs, including custom-ISA based processors, high-speed interconnects and high-bandwidth I/Os.
• Own features end-to-end, from specification through RTL, integration, synthesis and debug.
• Collaborate with physical design teams on synthesis, timing closure and power optimization.
• Work with the verification team to ensure design correctness.
• Work with architect engineers to model workloads, analyze performance bottlenecks and validate AI inference use cases.

Required profile

• 7+ years of experience in ASIC/SoC RTL design.
• Strong debugging and root-cause analysis capability.

Required skills

• Strong Verilog/SystemVerilog coding skills.
• Solid understanding of synthesis, timing and power analysis.
• Experience with Lint/CDC/RDC flows.