Principal Hardware ASIC Architect - AI Inference Accelerators

About the role

NXP is looking for an experienced Hardware Architect in Hyderabad to lead the architecture of AI inference accelerators. The role owns complex blocks or subsystems from concept through silicon, balancing performance, power and area, and works closely with software, RTL, verification and physical design teams.

Key responsibilities

• Own the architecture of compute, memory, interconnect and high-speed interface subsystems in the AI inference chip, defining product features and capabilities
• Collaborate with software teams to co-optimize hardware for AI workloads, including quantization, sparsity, dataflow, scheduling and memory bandwidth
• Work with RTL designers to identify risks, review and guide RTL implementation, and collaborate with physical design on area/floorplan and timing targets
• Define and document interface specifications, control/status logic and pipeline structures
• Lead PPA analysis and trade-off discussions across RTL and architecture
• Build and maintain high-level architecture and performance models, validate them against RTL or emulation results and use them to guide RTL improvements

Required profile

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering or a related field
• 12+ years of experience in SOC design, SOC architecture, RTL design and micro-architecture
• Proven experience optimizing for performance, power and area
• Strong understanding of computer architecture, memory hierarchies, SoC interconnects and AI/ML compute architectures

Required skills

• Hands-on expertise in Verilog/SystemVerilog and C/C++
• Scripting with Python, Tcl or Perl
• Preferred: experience with AI accelerators, DSPs or high-performance CPUs/GPUs, performance modeling frameworks, EDA tools and hardware-software co-design