Senior RTL Design & Integration Engineer

About the role

In this role you will help shape the future of AI/ML hardware acceleration by driving the development of Google’s Tensor Processing Unit (TPU) technology. You will work on custom silicon solutions that power demanding AI/ML applications in Google Cloud.

Key responsibilities

• Design, implement and integrate chassis, subsystems and system‑on‑chip (SoC) components for TPU accelerators.
• Develop and verify complex digital designs using Verilog/SystemVerilog, focusing on performance and power trade‑offs.
• Collaborate with Architecture, Verification, Power & Performance, and Physical Design teams to deliver high‑quality ASIC designs.
• Own medium‑complex SoC integration projects and quality control, including tape‑out and bring‑up activities.
• Drive micro‑architecture innovation and evaluate design choices for next‑generation AI/ML accelerators.

Required profile

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science or related field (or equivalent practical experience).
• At least 8 years of experience in digital logic design, RTL design, and integration of chassis, subsystems and SoC.
• Proven experience with logic synthesis, low‑power design, and verification of ASICs.
• Preferred: Master’s or PhD with 10 years of industry experience, ownership of complex SoC integration, and scripting experience (Python or Perl).

Required skills

• Verilog and SystemVerilog
• Digital logic and RTL design
• Logic synthesis and low‑power design techniques
• ASIC and SoC integration
• Python or Perl scripting
• Tape‑out and bring‑up support
• Knowledge of arithmetic units, bus architectures, processor design, accelerators and memory hierarchies