Senior Principal - IP Design

About the role

NXP is looking for a highly motivated, energetic and team-oriented Senior Principal to drive roadmaps for IP and subsystem domains, including the full IP portfolio, with a focus on logic design and the architecture and development of complex IPs and subsystems. The role works closely with a team of global experts in systems and SoC design to lead design and architectural challenges, and spans high-level specifications to implementation.

Key responsibilities

• Own and drive roadmaps for complete IP/subsystem portfolios within the global R&D team.
• Benchmark against industry players and deliver differentiating features for customers with a high level of innovation.
• Architect and design complex IPs and subsystems for edge processing, automotive self-driving vehicles, in-vehicle experience, gateway systems and fail-safe subsystems (ASIL-D).
• Lead IP and subsystems from concept through design and development, meeting aggressive, market-driven schedules.
• Ensure quality throughout the IP development cycle, analyse existing processes and implement improvements for zero-defect designs, while mentoring teams.
• Drive global IP design methodologies across sites with global stakeholders.

Required profile

• 18+ years of experience architecting and designing complex IP and subsystems with minimal supervision.
• Self-starter who can work independently and leads with ownership, trust and respect.
• Emotional intelligence and leadership, able to work locally, remotely and across multiple sites.

Required skills

• Custom processor designs (DSP for vision and radar) and processor designs such as RISC-V cores and cache-based subsystems.
• High-speed serial protocols (PCIe, Ethernet, MIPI CSI-2) and external memory interfaces (DDR4/LPDDR4, QuadSPI Flash).
• Microcontroller architecture and bus protocols (AHB/AMBA, AXI).
• Hands-on HDL (Verilog/VHDL), scripting (Perl, Tcl) and C/C++ for hardware modeling.
• End-to-end IP flow, including CDC/RDC, synthesis, DFT ATPG coverage, testbench and test plan development.
• Pre-silicon validation on FPGA/emulation boards is a significant advantage.