Senior / Lead Physical Design Engineer

About the role

We are seeking a highly experienced Senior/Lead Physical Design Engineer to drive backend implementation, sign‑off quality, and methodology development across our ASIC programs. The role combines technical leadership with hands‑on execution, guiding work from RTL handoff through tape‑out for our Trusted Control/Compute Unit (TCU) products.

Key responsibilities

• Lead physical design activities from project planning through tape‑out, defining implementation strategies, milestones and execution plans.
• Own block and full‑chip implementation tasks including floorplanning, power planning, placement, CTS, routing, timing closure, ECO and sign‑off closure.
• Define and drive sign‑off methodology, leading DRC, LVS, ERC, antenna, density and manufacturing rule closure.
• Develop and improve physical design methodologies, automation flows and best‑practice checklists.
• Collaborate with architecture, RTL, DFT, verification, packaging and CAD teams to influence design decisions and mitigate risks.

Required profile

• B.S./M.S. in Electrical Engineering or related field with 8–12 years of ASIC physical design experience.
• Multiple successful tape‑outs in advanced technology nodes and proven ownership from RTL handoff to GDS sign‑off.
• Experience leading projects, reviewing deliverables and coordinating across contractors and external vendors.

Required skills

• ASIC physical design (floorplanning, power planning, placement, CTS, routing, timing closure, ECO).
• Physical verification tools: Calibre, IC Validator (ICV) – DRC, LVS, ERC, antenna, density.
• Scripting in Tcl and Python for flow automation.
• Advanced node experience (7nm/5nm/3nm and below) and low‑power implementation techniques.