ASIC Design Engineer

About the role

Axiado is seeking an experienced ASIC/SoC Design Engineer to join its Smart Edge SoC team in Hyderabad. You will work across the full SoC design flow, collaborating closely with architecture, verification, physical design, and software groups while reporting to the Director of Engineering.

Key responsibilities

• Develop and implement SoC designs, including micro‑architecture, RTL coding, synthesis, timing closure, and documentation.
• Optimize top‑level and block‑level performance, bandwidth, and power.
• Partner with FPGA engineers for early prototyping and validation.
• Support test program development, chip validation, and production‑maturity activities.
• Collaborate with firmware, software, DV, FPGA, DFT, integration, and backend teams throughout ASIC development.

Required profile

• 8+ years of experience in RTL logic design, verification, synthesis, and timing optimization.
• Proficiency in writing clear micro‑architecture specifications and efficient Verilog RTL code.
• Strong understanding of assertions, coverage analysis, and timing closure.
• Hands‑on experience with interface protocols such as PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART.
• Experience bringing up and debugging designs on FPGA emulation platforms (e.g., HAPS, Veloce) and at least one tape‑out.
• Fluency in scripting languages like Perl and Python; familiarity with Bitbucket/Jenkins and JIRA is a plus.

Required skills

• Verilog RTL design and SoC integration.
• Micro‑architecture specification.
• Assertions, coverage analysis, synthesis, timing closure.
• Interface protocols: PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART.
• FPGA prototyping (HAPS, Veloce) and silicon bring‑up.
• Scripting: Perl, Python.
• Version control and CI tools: Bitbucket, Jenkins; issue tracking: JIRA.