Senior Lead Engineer - Memory Design (NVM IP)

About the role

NXP is looking for a Senior Lead Engineer in memory design to join its NVM IP design group in Bangalore, India. The role leads and manages a diverse NVM IP portfolio, develops and maintains automated IP management solutions, and works with third-party NVM IP vendors and NXP product design teams to deliver scalable NVM IP solutions across several business verticals.

Key responsibilities

• Benchmark NVM IP against product and technology requirements
• Prepare and verify IP design kits, then release them to product teams
• Support product design teams with NVM IP integration and troubleshooting
• Build and maintain an automated IP onboarding and release flow
• Maintain a portfolio of third-party and proprietary NVM IP from 180nm to 5nm
• Work directly with third-party vendors and silicon foundries
• Collaborate with the NXP NVM design teams in Bangalore, Europe and the US
• Drive the full NVM IP development lifecycle, coordinating with digital design, reliability and test engineering leads
• Track progress, report to stakeholders and mentor junior engineers

Required profile

• BS or MS in Electronics or Electrical Engineering
• 7+ years of experience in analog design, memory design (SRAM/NVM) or foundation IP design (IO/standard cells)
• Experience leading cross-functional teams across the full lifecycle, from requirements to GDS implementation
• Excellent communication skills and experience working with multi-site teams

Required skills

• Scripting and flow automation
• Quality-managed design flows, tools and methodologies (Cadence and Synopsys)
• Knowledge of NVM technology, macro architecture and design is a significant advantage