Principal Hardware DFT Lead

About the role

NXP is looking for a Principal Hardware DFT Engineer who will architect, implement and validate automotive-grade products. The role covers advanced test strategies, verification and validation of pre- and post-tapeout DFT features, test coverage improvements, and close collaboration with RTL and physical teams on DFT timing constraints and closures.

Key responsibilities

• Define and implement advanced DFT strategies, including scan architecture, JTAG, Memory BIST (MBIST) and Logic BIST (LBIST)
• Lead integration of digital subsystems, perform scan insertion and generate ATPG patterns to achieve high fault coverage
• Drive post-silicon validation and debug to root cause failures and improve manufacturing test efficiency
• Work with physical design and test engineering teams to ensure timing closure and that test patterns are ready when silicon arrives

Required profile

• B.S./M.S. in Electrical or Computer Engineering (or similar)
• 10+ years of industry experience in SoC DFT implementation, verification, static timing closure, test coverage analysis and improvement, and silicon bring-up on ATE

Required skills

• DFT: scan insertion and architecture, ATPG, MBIST and LBIST, boundary scan and JTAG, test compression
• HDL: Verilog or SystemVerilog for inserting test logic and writing test wrappers
• Timing: Static Timing Analysis and DFT-specific timing constraints (SDC files)
• EDA tools: Synopsys TestMAX/DFT Compiler, Mentor Graphics Tessent, Cadence Modus
• Scripting: Tcl, Python or Perl to automate test insertion flows, simulations and coverage reports