Principal Engineer - IP Verification

About the role

NXP is looking for a highly motivated, technically strong and execution-focused Individual Contributor to lead and deliver first-pass success for complex Digital IP and Subsystem verification programs. The role requires deep expertise in advanced verification methodologies, strong ownership and the ability to collaborate across multi-disciplinary and global teams. The engineer works closely with System Architecture, Design, DFT, Mixed Signal and Validation teams across sites on verification challenges spanning IP, Subsystem and full SoC contexts, using simulation, formal verification, hardware modeling and pre/post silicon validation.

Key responsibilities

• Lead end-to-end verification execution for complex IPs and Subsystems, ensuring high quality and first-pass silicon success
• Evaluate, adopt and deploy advanced and scalable verification methodologies to handle increasing design complexity
• Own verification quality metrics across planning, execution and closure phases
• Drive a 'Zero Defect' mindset through process adherence, coverage closure and defect prevention
• Analyze existing verification flows and improve their efficiency, predictability and quality
• Contribute to technical innovation, including methodology evolution and automation
• Collaborate with local and global cross-functional teams including Design, DFT, Architecture and Validation
• Support pre-silicon and post-silicon validation where required

Required profile

• 10-15 years of hands-on experience in IP or Subsystem verification for complex, multi-million gate designs
• Strong experience in testbench architecture, development, debugging and verification closure
• Experience in memory subsystems including SRAM, Flash, DDR and memory controllers
• Good to have: formal verification, gate-level simulation tools, emulation and pre-silicon validation environments, and domain knowledge in automotive, graphics/vision accelerators, high-speed serial interfaces or networking protocols such as Ethernet

Required skills

• HVLs: SystemVerilog/UVM and C/C++
• HDLS: Verilog/VHDL
• Simulators: VCS, NCSim, ModelSim or Questa
• Assertions (SVA), functional coverage and regression management
• Microcontroller architectures (ARM cores) and interconnect protocols (AHB, AXI, AMBA)