Lead Standard Cell Design & Characterization Engineer

About the role

NXP's Logic Library team is responsible for standard cell library solutions, including differentiated IP augmentation and internalization of third-party library IPs, and advises design teams on reliability, DfT and timing closure. This lead role covers characterization, layout design and EDA development of standard cells, and requires at least 7-9 years of experience in the standard cell domain.

Key responsibilities

• Characterize, layout and develop standard cell libraries, including flip-flops, latches, multibit flip-flops, level shifters, power switch cells, retention flops and synchronizer cells in planar and non-planar nodes.
• Contribute to improving and developing circuit design and standard cell library characterization.
• Implement innovative solutions within standard cell library development.
• Develop EDA views including characterization of NLDM, CCSP, CCSN and AOCV, LVF models; exposure to AOCV and LVF model characterization is a plus.

Required profile

• At least 7-9 years of experience in standard cell design, characterization and/or layout.
• Experience with planar and non-planar technology nodes.
• Knowledge of CMOS and FinFET technologies.
• Understanding of RTL-to-GDS flow (STA, PnR).

Required skills

• EDA tools from Siemens, Cadence and Synopsys for simulation, characterization and layout.
• Circuit and MC simulation, layout-dependent effects.
• Added advantage: MS Excel, PowerBI/Tableau, and scripting in SKILL, Python, TCL or Perl.