Lead DFT Engineer - SoC/ASIC

About the role

NXP is looking for an experienced and highly motivated Lead DFT Engineer with strong expertise in Design-for-Test methodologies for complex SoC/ASIC designs. The role drives complete DFT implementation and signoff from RTL to silicon validation, working closely with Design, Physical Design, Verification and Post-Silicon teams to ensure high test coverage, manufacturability and robust silicon quality.

Key responsibilities

• Lead end-to-end DFT implementation for SoC subsystems
• Drive DFT RTL integration and verification activities
• Manage cross-functional coordination for DFT deliverables at block and subsystem level
• Implement full-scan DFT methodologies and develop and optimize scan insertion and compression techniques
• Execute ATPG flows to achieve required fault coverage
• Define and implement MBIST architectures, including repair flows
• Support LBIST planning and implementation
• Ensure compliance with Boundary Scan / JTAG requirements
• Apply low-power DFT methodologies
• Perform testability analysis and improve design coverage
• Support silicon debug and failure analysis

Required profile

• B.Tech / M.Tech in Electronics, Electrical or a related field
• 5-8 years of experience in core DFT
• Strong problem-solving and debugging skills
• Ability to work in a cross-functional team environment
• Good communication and mentoring skills

Required skills

• Strong expertise in ATPG and LBIST methodologies
• Solid hands-on experience in scan insertion and compression
• Hands-on experience with iJTAG (IEEE 1687)
• Experience with MBIST architectures and repair flows
• Understanding of Boundary Scan / JTAG standards (1149.1, 1500, 1687 preferred)
• Exposure to low-power DFT concepts
• Experience in testability analysis and silicon debug