UVM Verification Specialist

About the role

We are seeking highly skilled UVM Verification specialists to join our dynamic team and support cutting‑edge projects in the telecom sector. This role offers the chance to work on complex ASIC and FPGA designs, applying advanced verification methodologies to ensure world‑class quality and performance.

Key responsibilities

• Perform ASIC verification using UVM and SystemVerilog.
• Develop and execute test plans, test benches, and verification environments.
• Verify IP blocks and multi‑clock domain designs.
• Collaborate with design teams to achieve functional correctness and coverage goals.
• Apply formal verification techniques and continuously improve verification processes.
• Debug and resolve issues efficiently under tight timelines.

Required profile

• Minimum 7 years of experience in ASIC/FPGA verification.
• Strong expertise in UVM methodology and SystemVerilog.
• Hands‑on experience with complex ASIC or large FPGA designs and multi‑clock domains.
• Knowledge of formal verification tools and techniques.
• Ability to create comprehensive coverage models and write immediate and concurrent assertions.

Required skills

• UVM
• SystemVerilog
• Formal verification
• ASIC and FPGA verification
• Multi‑clock domain verification
• IP block verification
• Coverage modeling
• AXI, AXIS, Avalon‑MM, Avalon‑ST, AHB, APB, Ethernet protocols
• C, Python, Perl, Bash, HLS
• Constrained randomization