UVM Verification specialist for ASIC and FPGA development

About the role

AFRY is seeking highly skilled UVM Verification specialists to join a dynamic team working on complex ASIC and FPGA designs for telecom projects. The role involves applying advanced verification methodologies to ensure world‑class quality and performance.

Key responsibilities

• Perform ASIC verification using UVM and SystemVerilog.
• Develop and execute test plans, test benches, and verification environments.
• Work on IP block verification and multi‑clock domain designs.
• Collaborate with design teams to ensure functional correctness and coverage goals.
• Apply formal verification techniques and contribute to continuous improvement of verification processes.
• Debug and resolve issues efficiently under tight timelines.

Required profile

• Minimum 5 years of experience in ASIC/FPGA verification.
• Strong expertise in UVM methodology and SystemVerilog.
• Hands‑on experience with complex ASIC or large FPGA designs.
• Experience in multi‑clock domains and IP block verification.
• Knowledge of formal verification tools and techniques.
• Analytical mindset, results‑oriented, able to work independently and as a team player.

Required skills

• UVM, SystemVerilog, ASIC verification, FPGA verification.
• Formal verification, coverage modeling, concurrent assertions.
• Familiarity with protocols such as AXI, AXIS, Avalon‑MM, Avalon‑ST, AHB, APB, Ethernet.
• Programming/scripting: C, Python, Perl, Bash, HLS.
• Constrained randomization.