Staff/Senior Staff Physical Design Engineer – Technical Lead

About the role

EnCharge AI is looking for a high‑impact Staff/Senior Staff Physical Design Engineer to act as a Technical Lead for next‑generation silicon products. This "player‑coach" position requires both architectural vision for convergence strategies and hands‑on mentorship of a small engineering team. You will own the physical delivery of a major sub‑chip or complex block, driving the limits of Power, Performance, and Area while ensuring tape‑out milestones are met.

Key responsibilities

• Technical Leadership – guide a small team of PD engineers, manage workload, and provide architectural oversight for a sub‑chip or partition.
• Complex Block Ownership – take hands‑on responsibility for critical, high‑congestion or timing‑critical blocks.
• Timing & PPA Strategy – architect custom PPA recipes beyond standard vendor flows to achieve aggressive targets.
• Advanced Automation – develop sophisticated Tcl and Python scripts for flow automation, data mining, and sign‑off verification.
• Stakeholder Management – collaborate with RTL, DFT, and Synthesis teams, communicating risks and driving left‑shift optimizations.
• Sign‑off Accountability – ensure the sub‑chip meets all sign‑off criteria, including STA, EM/IR (Voltus/Apache), and Physical Verification (Pegasus/Calibre).

Required profile

• High workability and assertiveness – proactive communicator who can hold ground on technical requirements while staying collaborative.
• Analytical problem solver – identifies root causes of violations and implements systemic fixes.
• Driven and versatile – ready to jump into any part of the flow, from floorplan to GDSII, to unblock the team.
• Mentorship – passionate about raising the technical bar for reporting engineers.

Required skills

• Expert‑level proficiency with Cadence Innovus and Cadence Tempus.
• Deep expertise in Static Timing Analysis (STA), multi‑corner sign‑off, and crosstalk closure.
• Advanced node PPA optimization (7nm, 5nm or below) including custom floorplanning and CTS strategies.
• Advanced scripting in Tcl and Python for automation and methodology development.
• Experience with EM/IR tools (Voltus, Apache) and physical verification tools (Pegasus, Calibre).