Staff ASIC Design Engineer

About the role

Axiado is looking for a talented Staff ASIC Design Engineer to join its Hyderabad team. You will own critical ASIC projects, drive System‑on‑Chip (SoC) development, and see designs through from concept to production maturity. The role requires close collaboration with firmware, software, verification, FPGA, DFT and backend teams.

Key responsibilities

• Design and implement RTL blocks with micro‑architecture optimization.
• Develop comprehensive micro‑architecture specifications and technical documentation.
• Perform synthesis, timing closure, and power optimization to meet target metrics.
• Collaborate with cross‑functional teams throughout ASIC development.
• Support prototyping, test program development, and chip validation from bring‑up to production.
• Conduct FPGA‑based emulation debugging and resolve complex issues.
• Implement and analyze assertions and coverage metrics for design quality.
• Mentor junior engineers and guide best‑practice methodologies.

Required profile

• 7+ years of hands‑on RTL logic design, verification, synthesis and timing optimization.
• Proven expertise in Verilog RTL coding and SoC integration.
• Experience delivering at least one full tape‑out cycle and silicon validation.
• Strong communication and documentation skills for cross‑team collaboration.
• Ability to work independently and solve complex technical problems.

Required skills

• Verilog RTL design
• Synthesis and timing closure
• PCIe, USB, Ethernet, DDR/LPDDR4/5, I2C/I3C, eSPI, SPI interfaces
• FPGA emulation platforms (HAPS, Veloce)
• Perl and Python scripting
• Bitbucket, Jenkins, JIRA