SOC Design Implementation Engineer

About the role

As a SOC Design Implementation Engineer at Qualcomm, you will be responsible for implementing and optimizing system‑on‑chip designs, ensuring high performance, low power and area efficiency. You will work closely with design, DFT and product development teams to bring silicon concepts to silicon.

Key responsibilities

• Perform RTL synthesis to achieve optimal performance, power and area.
• Insert DFT features such as MBIST and scan chains, and set up timing constraints for functional and test modes.
• Run static low‑power checks on gate‑level netlists.
• Verify logic equivalence between RTL and gate‑level representations.
• Set up sign‑off static timing analysis (STA) and ECO flows, and drive timing closure.
• Conduct timing analysis using STA tools, debug constraints and perform sanity checks.

Required profile

• Bachelor’s degree in Computer Science, Electrical/Electronics Engineering or related field with 2+ years of hardware engineering experience, or a Master’s degree with 1+ year, or a PhD with relevant experience.

Required skills

• RTL synthesis
• Design‑for‑test (DFT) insertion, including MBIST and scan
• Static low‑power verification
• Logic equivalence checking (RTL ↔ gate)
• Static timing analysis (STA) and ECO flow management
• Timing closure and constraint debugging