Senior Principal Engineer - IP Verification

About the role

NXP is looking for a highly motivated, energetic, team-oriented individual contributor to deliver first-pass success of complex IPs using advanced verification languages and methodology. The engineer works with experienced global stakeholders in Systems, Design, DFT, Mixed Signal and other local and remote teams, addressing verification challenges at IP, subsystem and system levels through simulation, hardware modeling, formal verification and pre/post silicon validation.

Key responsibilities

• Evaluate and deploy evolving verification methodologies for complex IP/subsystem designs within aggressive, market-driven schedules.
• Own and ensure quality adherence throughout the project cycle, and analyse existing processes to recommend and implement improvements for zero-defect IPs/subsystems.
• Build and influence technological innovations for yourself and the team, working with global stakeholders across sites.
• Work hands-on as part of local, remote and multi-site teams.

Required profile

• 18+ years of experience in IP/subsystem verification on multimillion-gate, complex designs with multiple clocks, with minimal supervision.
• End-to-end IP verification project cycle experience, including testbench strategies, TB development and simulation debugging.
• Ability to drive verification methodologies is highly desired for candidates with 10+ years of experience.

Required skills

• Testbench and testplan development, features traceability, and microcontroller architecture with ARM cores, AHB/AMBA, AXI, Flash, SRAM, DDR and memory controllers.
• HVLs such as UVM, SystemVerilog and C++, HDLs Verilog/VHDL, PLI/DPI, and simulators NCSim, VCS, ModelSim and Questa.
• Formal verification, assertions/SVA, functional coverage, gate-level simulation, verification planning and regression management.
• Exposure to pre-silicon validation/emulation is an added advantage.