Senior Principal Digital IP Engineer

About the role

NXP is looking for a Senior Principal Digital IP Engineer in Bangalore. You will develop high-quality, reusable IPs for SoC and subsystem integration and drive designs from concept through silicon, working on cutting-edge semiconductor technologies with global cross-functional teams.

Key responsibilities

• Work with architecture teams and define the micro-architecture based on IP requirements
• Develop RTL using Verilog, SystemVerilog or VHDL according to micro-architectural specifications
• Optimize designs for power, performance and area
• Run design checks such as lint, CDC, synthesis and static timing analysis
• Drive bug fixing and closure
• Support design reviews and sign-off processes
• Collaborate with verification teams on test plans and coverage closure

Required profile

• Strong experience in RTL design (Verilog, SystemVerilog, VHDL)
• Solid understanding of SoC and IP design and integration
• Hands-on experience with lint, CDC, synthesis and timing analysis
• Experience in low-power design techniques

Preferred skills

• Full-cycle IP/SoC development
• Formal verification or low-power flows
• Post-silicon validation and bring-up