Senior Lead Engineer - IP Design

About the role

NXP is looking for a highly motivated, energetic and team-oriented Senior Lead Engineer in IP Design in Bangalore. The role drives roadmaps for IP and subsystem domains, including the full IP portfolio, and goes deeper into logic design while architecting and developing complex IPs and subsystems. It works closely with a team of global experts in systems and SoC design to solve architectural challenges, and spans high-level specifications to implementation.

Key responsibilities

• Own and drive roadmaps for complete IP/subsystem portfolios within the global R&D team.
• Benchmark against industry players and deliver differentiating features for customers with a high level of innovation.
• Architect and design complex IPs and subsystems for edge processing, automotive self-driving vehicles, in-vehicle experience, gateway systems and fail-safe subsystems (ASIL-D).
• Lead IP and subsystems from concept through design and development, meeting aggressive, market-driven schedules.
• Ensure quality throughout the IP development cycle, analyse existing processes and implement improvements for zero-defect designs, mentoring teams.
• Drive global IP design methodologies across sites with global stakeholders.

Required profile

• 8 to 12 years of experience architecting and designing complex IP and subsystems with minimal supervision.
• Self-starter who can work independently and leads teams locally and remotely or across multiple sites.
• Strong written and verbal communication, ownership, trust and respect, emotional intelligence and leadership values.

Required skills

• High-speed serial protocols and controller and PHY challenges for PCIe, Ethernet and SerDes.
• External memory interfaces such as DDR4/LPDDR4 and QuadSPI Flash.
• Microcontroller architecture and bus protocols such as AHB/AMBA and AXI.
• Hands-on HDL (Verilog/VHDL), scripting (Perl, Tcl) and C/C++ for hardware modeling.
• End-to-end IP flow, including CDC/RDC, synthesis, DFT ATPG coverage, testbench and test plan development.
• Pre-silicon validation on FPGA/emulation boards is a significant added advantage.