Senior IC Packaging Engineer

About the role

Axiado is building AI‑powered digital infrastructure and is looking for a Senior IC Packaging Engineer to provide technical leadership and architectural ownership of advanced IC and System‑in‑Package (SiP) solutions. The role combines deep hands‑on expertise with system‑level thinking in a fast‑growing startup environment.

Key responsibilities

• Serve as the technical authority for IC and SiP packaging across multiple products and programs.
• Own package architecture and technology roadmap aligned with product cost and scalability goals.
• Lead chiplet‑based packaging strategies, including UCIe, silicon interposers, and advanced RDL.
• Perform hands‑on package design and physical layout for high‑speed SerDes/PHY, LPDDR5, PCIe, CXL and other multi‑gigabit interfaces.
• Define substrate stack‑ups, materials, bump/RDL architectures, and DFM guidelines for advanced nodes.
• Drive SI/PI, thermal, mechanical and reliability trade‑offs at system and package levels.
• Lead external engagement with OSATs, foundries and key suppliers for technology development and manufacturing readiness.
• Influence product roadmap, risk management and investment decisions through technical insight.

Required profile

• BSEE or MSEE (PhD a plus) in Electrical Engineering or related field.
• 10+ years of experience with extensive IC packaging expertise for SoCs, ASICs or memory products.
• Deep hands‑on expertise in Flip‑Chip BGA, SiP, RDL, silicon interposers and chiplet architectures (UCIe).
• Strong understanding of electrical, mechanical, thermal and reliability design trade‑offs.
• Proven ability to operate autonomously, make high‑impact decisions and execute in a startup environment.

Required skills

• Flip‑Chip BGA (FCBGA) and System‑in‑Package (SiP) design.
• RDL, silicon interposers and UCIe chiplet integration.
• High‑speed SerDes package development (PCIe Gen5, LPDDR5, USB 3.x, 10G interfaces).
• Cadence Allegro Package Designer (APD) or equivalent EDA tools.
• SI/PI analysis using HFSS, SIwave or Ansys Designer.
• Design‑for‑Manufacturing (DFM) and yield optimization.