Senior CAD Engineer - Digital Verification

About the role

NXP is looking for a Senior CAD Engineer specializing in Digital Verification in Noida. The role builds, enhances and supports scalable verification infrastructure, methodologies and EDA automation flows for ASIC/SoC development, giving verification teams robust regression systems, automation frameworks and advanced methods such as UVM, coverage and continuous integration flows.

Key responsibilities

• Act as the main support interface for Design and Verification teams, troubleshooting simulation, regression, coverage and debug issues
• Help DV teams adopt modern techniques (coverage-driven, formal, emulation) and deploy, integrate and maintain CAD tools, scripts and environments
• Provide day-to-day support for EDA tools (VCS, Xcelium, Verdi, vManager) and work with vendors (Cadence, Synopsys, Siemens) to debug and escalate tool issues
• Support and maintain regression and CI/CD systems, and monitor and optimize compute farms and LSF environments
• Analyze DV flow issues and performance bottlenecks, and partner with DV, RTL design and system teams on cross-functional problems
• Guide verification engineers, train them on tools and flows, and maintain documentation and best practices

Required profile

• Bachelor's or master's degree in Electronics Engineering
• 8-12 years of experience in Digital Verification, CAD or engineering support roles
• Strong understanding of the digital verification flow (simulation, regression, coverage, debug)
• Hands-on experience with System Verilog and UVM from a debugging/support perspective
• Linux environment experience and familiarity with SoC/ASIC architecture and RTL concepts
• Ability to work in multi-cultural global environments with globally distributed teams

Required skills

• EDA tools: VCS, Xcelium, Verdi, vManager
• Scripting/programming in Python, Tcl, Perl or similar
• Regression environments, CI/CD systems and compute farm usage
• AI/ML-based DV tools (e.g. Cadence Verisium AI) is a plus