Senior ASIC Verification Engineer

About the role

Axiado is seeking a Senior ASIC Verification Engineer to lead verification efforts for ARM‑based SoCs and subsystems. You will work on RTL verification using industry‑standard methodologies such as UVM, portable stimulus, and formal verification, reporting to the Director of Engineering (Verification). This role is critical to delivering secure, AI‑enabled hardware for edge and data‑center applications.

Key responsibilities

• Lead test‑plan definition, micro‑architecture verification, and documentation for top‑level and block‑level functional and performance verification.
• Develop and maintain UVM environments, support test program development, and drive chip validation through production maturity.
• Collaborate with firmware, software, DV, FPGA, DFT, SoC integration, and backend teams across ASIC development stages.
• Perform system‑level use‑case verification and support post‑silicon bring‑up and debugging.

Required profile

• 8+ years of experience in UVM verification and environment development.
• BE/BTECH or ME/MTECH degree in EE/EECS/CS or equivalent.
• Proven ability to develop test plans and test cases in C, Assembly, and SystemVerilog.
• Strong understanding of coverage analysis, performance verification, and use‑case verification.

Required skills

• UVM methodology, SystemVerilog, C/Assembly test development.
• Experience with AMBA AXI, AHB, APB protocols and interface protocols such as PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART.
• Functional test vector creation and post‑silicon bring‑up/debug.
• Scripting in Perl, Python, Shell; repository tools Bitbucket, Jenkins; bug tracking with JIRA.