Principal Verification Engineer - Digital IP (G4)

About the role

NXP is looking for a highly motivated, technically strong and execution-focused Individual Contributor to lead and deliver first-pass success for complex Digital IP and Subsystem verification programs. The role works closely with System Architecture, Design, DFT, Mixed Signal and Validation teams across sites, using simulation, formal verification, hardware modeling and pre/post silicon validation techniques.

Key responsibilities

• Lead end-to-end verification execution for complex IPs and Subsystems, ensuring high quality and first-pass silicon success
• Evaluate, adopt and deploy advanced and scalable verification methodologies as design complexity grows
• Own verification quality metrics across planning, execution and closure phases
• Drive a 'Zero Defect' mindset through process adherence, coverage closure and defect prevention
• Analyze existing verification flows and improve their efficiency, predictability and quality
• Contribute to technical innovation, including methodology evolution and automation
• Collaborate with local and global cross-functional teams (Design, DFT, Architecture, Validation)
• Support pre-silicon and post-silicon validation where required

Required profile

• 10-15 years of hands-on experience in IP or Subsystem verification for complex, multi-million gate designs
• Strong expertise in HVLs such as SystemVerilog/UVM and proficiency in C/C++
• Solid understanding of microcontroller architectures (ARM cores) and interconnect protocols (AHB, AXI, AMBA)
• Experience in memory subsystems (SRAM, Flash, DDR, memory controllers)
• Soft skills: customer focus, ownership and accountability, collaboration, and an innovation mindset

Required skills

• Industry simulators: VCS, NCSim, ModelSim or Questa
• Testbench architecture, development, debugging and closure
• Test planning, feature traceability, functional and performance validation
• Assertions (SVA), functional coverage and regression management
• Good to have: formal verification, gate-level simulation tools, emulation and pre-silicon validation environments, and domain knowledge in automotive, graphics/vision accelerators, high-speed serial interfaces or networking protocols