STA Methodology Engineer

About the role

NXP is looking for an experienced STA Methodology Engineer to join its CTO-DE-FDIP-Logic Libraries team in Bengaluru. The role benchmarks logic libraries across multiple technology nodes (40nm, 14nm, 10nm, 7nm, 5nm) using synthesis and PNR-based flows on real chips and blocks, working closely with the Timing Methodology and Signoff teams.

Key responsibilities

• Benchmark logic libraries across advanced technology nodes using synthesis and PNR flows.
• Collaborate with cross-functional teams to validate and refine timing constraints.
• Develop and maintain benchmarking frameworks for constraint validation and STA methodology evaluation.
• Perform STA including timing analysis, DRCs, annotation issues, multivoltage flow enablement, noise and crosstalk analysis via Logic Libraries integration flow checks.
• Contribute to the development and automation of STA flows and methodologies.

Required profile

• Bachelor's or Master's degree in Electrical or Electronics Engineering.
• 10-12 years of hands-on STA experience, with proven tape-out experience as a block owner or lead.
• Deep understanding of STA concepts, timing constraints and closure methodologies at block and SoC level.
• Strong collaboration skills and ability to work across teams; self-motivated, proactive problem solver, able to work independently and in a global team.

Required skills

• Handling timing issues such as DRCs, annotation, multivoltage flows, noise and crosstalk.
• Preferred: Python scripting, experience developing STA flow automation, familiarity with industry-standard EDA tools and flows.
• Preferred: understanding of AI/GenAI.