Senior RTL Engineer – Silicon Design for AI/ML Accelerators

About the role

As a Senior RTL Engineer you will help shape the future of AI/ML hardware acceleration by driving the development of Google’s Tensor Processing Unit (TPU) silicon. You will work on custom ASIC/SoC designs that power data‑center accelerators and collaborate across architecture, verification, power, and physical design teams.

Key responsibilities

• Own micro‑architecture and RTL implementation of complex IP blocks and subsystems.
• Perform quality checks, code reviews, and contribute to design methodology and libraries.
• Drive power, performance and area (PPA) improvements and participate in synthesis, timing and power closure.
• Collaborate with verification and physical design teams to ensure successful silicon bring‑up.
• Participate in FPGA prototyping and silicon bring‑up activities.

Required profile

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science or related field, or equivalent practical experience.
• 8+ years of ASIC/SoC development experience using Verilog/SystemVerilog.
• Experience in micro‑architecture, IP and subsystem design, and ASIC verification.
• Proven experience with synthesis, timing/power analysis and Design‑for‑Testing.
• Preferred experience with Python, C/C++ or Perl programming, and SoC integration flows.

Required skills

• Verilog / SystemVerilog
• ASIC / SoC design and verification
• Micro‑architecture and IP development
• Synthesis, timing and power analysis
• Design‑for‑Testing (DFT)
• Python, C/C++, Perl
• FPGA prototyping and silicon bring‑up