Senior Manager, Design Verification Engineering

About the role

Analog Devices is seeking a Senior Manager, Design Verification Engineer to lead a multifunctional team responsible for design verification of highly integrated solutions and products. The role drives real revenue growth on next-generation edge intelligence products across several business units, leading pre-silicon verification of SoC or subsystem designs.

Key responsibilities

• Lead end-to-end SoC verification for complex digital SoCs, from planning to signoff, and verify microprocessor-based designs, AI/ML accelerators and high-speed peripherals
• Define the overall verification strategy, architecture, flow, methodology and test plans, and close functional and code coverage at block, subsystem and SoC levels
• Architect and implement scalable UVM-based testbenches, DV flows and methodologies, including NoC/interconnect verification and formal verification of IP and subsystems
• Work with emulation, FPGA, firmware and system teams to cover post-silicon validation early, and drive performance verification and system-level analysis
• Mentor and guide the team, plan tasks and track progress, and contribute to cross-company technical initiatives, patents and publications

Required profile

• B.Tech/M.Tech with 12+ years of experience in digital pre-silicon verification, including leadership across IP, subsystem or SoC-level DV
• Proven track record of verification closure using functional and code coverage metrics
• Experience in security and safety verification, and familiarity with gate-level simulation with timing annotation
• Good communication and leadership skills, with travel required about 10% of the time; shift type is day shift

Required skills

• Verilog/SystemVerilog and UVM-based testbench development and debugging
• NoC, bus and interconnect verification, and coverage analysis
• Power-aware verification (UPF) and formal verification
• Protocol knowledge: I2C, SPI, Ethernet, UART, AXI/AHB, DMA, SVI3
• Processor-based systems (ARM, RISC-V, Tensilica), AI/ML accelerators, C/C++, SystemC, Python/TCL/Shell
• Mixed-signal/analog verification (ADC/DAC/PLL/PHY) is a plus