Staff Physical Design Engineer

About the role

Analog Devices is hiring a Staff Physical Design Engineer who combines deep hands-on implementation expertise with technical leadership. The role owns complex block- and/or top-level physical design for advanced-node SoCs and leads a small group of engineers to deliver high-quality results on time.

Key responsibilities

• Own end-to-end physical implementation (floorplanning, power planning, placement, CTS, routing, ECO) for complex blocks or subsystems across advanced nodes (22nm, 16nm, 7nm, 5nm, 4nm)
• Drive timing closure, congestion resolution, IR/EM, signal integrity and physical verification (DRC/LVS/antenna) to meet PPA and quality targets
• Define hierarchical PNR strategies, IO ring/PG structures and integration guidelines for large SoCs, and debug tool issues, timing failures and physical anomalies
• Develop, maintain and improve physical design methodologies, scripts and flows (PDN, PG, clock structure, signoff automation) and evaluate EDA tool features with CAD/enablement teams
• Lead a small group of engineers: break down tasks, set priorities, mentor juniors and NCGs in PNR, STA and debug, and review floorplans and constraints
• Work with RTL design, STA, DFT, CAD and packaging teams, communicate risks and trade-offs to project leads, and take part in design and signoff reviews

Required profile

• 8-12+ years in physical design or equivalent mastery of complex digital SoC implementation
• Proven success closing timing-, IR- and congestion-critical blocks on advanced nodes
• Strong problem-solving and debugging mindset, clear communication, and a commitment to mentoring and knowledge sharing
• Willingness to travel about 10% of the time; 1st shift, days

Required skills

• PNR and signoff tools such as Cadence Innovus, Synopsys ICC2, Tempus/PrimeTime, RedHawk, Voltus
• Floorplanning, power grid and PDN methodology (IR/EM mitigation)
• Clock tree/mesh design and STA constraints
• Physical verification and reliability checks