Senior DFT Engineer

About the role

Analog Devices is looking for a Senior DFT Engineer to define and implement DFT architecture for SoCs, covering scan, MBIST, JTAG and ATPG flows, and to support post-silicon bring-up and test cost and yield improvement. The role involves close collaboration with product, test, evaluation and physical design teams.

Key responsibilities

• Define DFT architecture: understand SoC architecture and test requirements, work with the lead Product/Test engineer to optimise test cost and coverage, and drive SCAN, MBIST, JTAG boundary scan and hierarchical scan.
• Implement and upgrade SCAN and MBIST insertion flows, set timing constraints for SCAN/MBIST modes and debug timing violations.
• Implement ATPG flows for various fault models, simulate SCAN, MBIST and BSCAN patterns, and provide solutions for testing analog macros.
• Support post-silicon bring-up with the Evaluation/Test Engineering team, handle failure analysis as required, and work with Operations on test cost and yield improvement.
• Keep DFT methodology aligned with industry best practices, work with the physical design team throughout the cycle, and mentor new team members.

Required profile

• 4-8 years of industry experience in DFT.
• Experience bringing at least one or two products from architecture through scan implementation and simulation to production.
• Hands-on experience with post-silicon activities.
• Exceptional interpersonal and communication skills for collaborating with product and CAD tool teams worldwide.

Required skills

• Preferred: Tessent DFT (SCAN, MBIST, LBIST, OCC, EDT, SSN, Boundary Scan).
• Scripting in Perl, Python or TCL and a good command of HDLs.
• Preferred: Cadence Genus and Tempus, timing closure and physical design experience, and exposure to deep submicron effects and UPF/CPF.