Principal Engineer, Design Verification Engineering

About the role

Analog Devices is looking for a Principal Engineer, Design Verification, to lead the design verification of highly integrated solutions and products in a multifunctional team. The role drives real revenue growth on next-generation edge-intelligence products across several products and business units. It leads the pre-silicon verification of SoC or subsystem designs and defines verification strategy, architecture, flow and methodology.

Key responsibilities

• Lead end-to-end SoC verification for complex digital SoCs, from planning to signoff, and verify microprocessor-based designs, AI/ML accelerators and high-speed peripherals.
• Define and drive team execution by planning tasks, tracking progress and providing technical leadership, mentoring and guidance.
• Collaborate with architecture and design teams on requirements and deliverables, and work with emulation, FPGA and software teams to cover post-silicon scenarios early.
• Develop system-level use cases, architect scalable UVM-based testbenches and DV flows, and define and review test plans with functional and code coverage closure.
• Apply formal verification, lead NoC/interconnect verification, and perform performance verification and system-level analysis.
• Drive innovation in verification strategies to meet aggressive schedules and quality goals, and take part in cross-company technical initiatives, patents and publications.

Required profile

• B.Tech/M.Tech with 12+ years of experience in digital pre-silicon verification, including leadership across IP, subsystem or SoC-level DV.
• Proven track record of verification closure using functional and code coverage metrics.
• Experience in security and safety verification, and familiarity with gate-level simulation with timing annotation.
• Good communication and leadership skills, able to collaborate across global teams; 25% travel required.

Required skills

• SoC/subsystem architecture, Verilog/SystemVerilog and UVM-based testbench development.
• NoC, bus and interconnect verification, and coverage analysis.
• Formal verification, constrained-random verification, assertions and transaction-level modeling.
• Power-aware verification (UPF) and protocol verification (I2C, SPI, Ethernet, UART, AXI/AHB, DMA, SVI3).
• Processor-based systems (ARM, RISC-V, Tensilica), AI/ML accelerators, and C/C++, SystemC and scripting (Python/TCL/Shell).
• Mixed-signal/analog verification (ADC/DAC/PLL/PHY) is a plus.