Principal Engineer, Design Verification (Digital Design)

About the role

Analog Devices is looking for a Principal Engineer, Design Verification (Digital Design) to lead the design verification of highly integrated solutions and products in a multifunctional team. The role drives real revenue growth on next-generation edge-intelligence products across several products and business units. It leads the pre-silicon verification of SoC or subsystem designs and is expected to lead and influence verification methodologies within both the DBU and ADI.

Key responsibilities

• Lead end-to-end SoC verification for complex digital SoCs, from planning to signoff, and verify microprocessor-based designs, AI/ML accelerators and high-speed peripherals.
• Define the overall verification strategy, architecture, flow and methodology, and lead and close verification of large integrated products.
• Plan tasks, track progress and provide technical leadership, mentoring and guidance to the team.
• Work with architecture and design teams on requirements and deliverables, and with emulation, FPGA and software teams on pre-silicon readiness.
• Develop system-level use cases, architect scalable UVM-based testbenches and DV flows, and define and review test plans.
• Ensure functional and code coverage closure across block, subsystem and SoC levels, and apply formal verification, NoC/interconnect verification and performance analysis.
• Participate in cross-company technical initiatives and contribute to patents and publications where possible.

Required profile

• B.Tech/M.Tech with 12+ years of experience in digital pre-silicon verification, including leadership across IP, subsystem or SoC-level DV.
• Proven track record of verification closure using functional and code coverage metrics.
• Experience in security and safety verification, and familiarity with gate-level simulation with timing annotation.
• Good communication and leadership skills, with ability to collaborate across global teams; 10% travel required.

Required skills

• Verilog/SystemVerilog and UVM-based testbench development and debugging.
• NoC, bus and interconnect verification, and coverage analysis.
• Formal verification, constrained-random verification, assertions and transaction-level modeling.
• Power-aware verification (UPF) and protocol verification (I2C, SPI, Ethernet, UART, AXI/AHB, DMA, SVI3).
• Processor-based systems (ARM, RISC-V, Tensilica), AI/ML accelerators, and C/C++, SystemC and scripting (Python/TCL/Shell).
• Mixed-signal/analog verification (ADC/DAC/PLL/PHY) is a plus.