Power-Domain Verification Lead

About the role

The Power‑Domain Verification Lead will drive power‑aware simulation and verification for Axiado’s AI‑powered digital infrastructure solutions. You will focus on RTL SoC/subsystem verification based on ARM CPUs, using industry‑standard methodologies such as UVM, Portable Stimulus and Formal verification to ensure low‑power functionality across power domains.

Key responsibilities

• Execute power‑aware simulations and debug failures related to power intent.
• Integrate UPF with UVM testbenches and VIPs.
• Verify designs at RTL (SOC) level and perform gate‑level simulations.
• Create directed and constrained‑random tests for low‑power scenarios.
• Validate power‑gating, isolation, retention, save/restore and reset behavior across power domains.
• Develop assertions and functional coverage for power states and transitions.
• Support power‑aware regression and sign‑off activities.
• Write and maintain scripts in Make, Perl, Python or Shell.
• Collaborate with RTL designers and power architects.

Required profile

• 10+ years of hands‑on experience with SystemVerilog and UVM.
• Strong understanding of UPF and power‑intent modeling.
• Experience with power‑aware simulation and low‑power verification.
• Knowledge of power domains, isolation, retention, level shifters and reset‑vs‑power interactions.
• Excellent debug skills across RTL, UPF and testbench environments.
• B.E./B.Tech or M.E./M.Tech degree in EE/EECS/CS or equivalent.

Required skills

• SystemVerilog
• UVM
• UPF (Unified Power Format)
• Power‑aware simulation
• RTL verification
• ARM CPU architectures
• Portable Stimulus
• Formal verification
• Make, Perl, Python, Shell scripting