Physical Design Engineer

About the role

We are seeking a motivated Physical Design Engineer to join Axiado’s ASIC team in Hyderabad. You will work on end‑to‑end backend implementation of cutting‑edge semiconductor chips, contributing to the Trusted Control/Compute Unit platform.

Key responsibilities

• Implement block‑level and subsystem‑level designs from netlist to GDS, including floorplanning, placement, CTS, routing and physical optimization.
• Analyze and resolve timing, congestion, utilization and routing issues, and support ECO and timing‑closure activities.
• Perform setup and hold timing analysis with PrimeTime or equivalent STA tools, debug violations and improve clock quality.
• Execute physical verification (DRC, LVS, ERC, antenna, density) using Calibre or ICV and prepare designs for tape‑out sign‑off.
• Optimize power, performance and area trade‑offs, implement low‑power techniques and support leakage reduction.
• Develop and maintain Tcl/Python scripts to automate flow steps and increase productivity.
• Collaborate with RTL, DFT, DV and other design teams, participating in design reviews and technical discussions.

Required profile

• Bachelor’s or Master’s degree in Electrical or Computer Engineering or related field.
• 2–5 years of ASIC physical design experience with at least one successful tape‑out.
• Strong hands‑on skills in floorplanning, placement, CTS, routing, timing closure and ECO implementation.
• Excellent debugging ability and curiosity to understand root causes.

Required skills

• Cadence Innovus, Synopsys ICC2, PrimeTime/Tempus, Calibre/ICV.
• Tcl scripting (required) and Python scripting (preferred).
• Experience with physical verification (DRC, LVS, ERC, antenna, density).
• Power, performance and area (PPA) analysis and optimization.