ASIC Verification Engineer (EEJ)

About the role

We are looking for an experienced ASIC Verification Engineer (EEJ) to join Bosch’s Bengaluru software centre. You will work on verification of automotive ASICs, SoCs and IP blocks, applying metric‑driven and formal verification techniques.

Key responsibilities

• Develop and maintain verification plans for ASICs, subsystems and IPs.
• Create verification environments from scratch, including VIP integration.
• Apply constrained‑random verification using SystemVerilog, UVM/OVM and functional coverage.
• Run regression suites, measure results and drive continuous improvement of verification flows.
• Collaborate with EDA partners and hardware teams to enhance tools, methodologies and processes.
• Participate in ASIC/SoC tape‑out cycles and support formal verification where needed.

Required profile

• 5‑10 years of digital RTL verification experience.
• Strong knowledge of SystemVerilog, UVM (or OVM) and constrained‑random verification.
• Hands‑on experience with Cadence, Synopsys or Mentor verification tools.
• Familiarity with AMBA protocols and ARM‑based subsystems.
• Experience with configuration management, bug‑tracking and scripting (Perl, TCL).
• Prior involvement in ASIC/SoC tape‑outs.

Required skills

• SystemVerilog
• UVM / OVM
• Cadence, Synopsys, Mentor tools
• Perl, TCL scripting
• AMBA protocols
• ARM processor verification
• VHDL, Verilog
• Formal verification (optional)
• SPECMAN (optional)