ASIC Verification Engineer (EEJ 2026)

About the role

We are looking for an experienced ASIC Verification Engineer to join Bosch’s Bengaluru development centre. The role focuses on verification of automotive ASICs, SoCs and IP blocks using industry‑leading methodologies.

Key responsibilities

• Develop and maintain verification plans and environments for SoCs, ASICs and IPs from scratch.
• Apply metric‑driven verification (MDV) and formal verification techniques where appropriate.
• Create and integrate Verification IP (VIP) components and ensure coverage goals are met.
• Run regression suites, analyse results and drive continuous improvement of verification flows.
• Collaborate with EDA partners and hardware teams to optimise tools and processes.

Required profile

• 5‑10 years of digital RTL verification experience using SystemVerilog and UVM.
• Hands‑on experience with Cadence, Synopsys or Mentor verification tools.
• Strong knowledge of constrained‑random verification, functional coverage and coverage analysis.
• Experience with configuration management, bug‑tracking systems and scripting (Perl, TCL).
• Participation in at least one ASIC/SoC tape‑out.

Required skills

• SystemVerilog
• UVM (or OVMS)
• Cadence, Synopsys, Mentor verification toolchains
• Perl, TCL scripting
• AMBA protocol verification
• ARM‑based subsystem/SoC verification
• VHDL/Verilog
• Formal verification (desirable)
• SPECMAN (desirable)

What we offer

• Opportunity to work on cutting‑edge automotive ASIC projects.
• Access to global Bosch resources and a collaborative engineering environment.
• Competitive compensation and benefits package.