ASIC Engineer

About the role

NVIDIA’s Global Flows Team is looking for an ASIC Engineer to develop and deploy advanced RTL design‑quality methodologies across its CPU programs. You will work at the intersection of digital implementation, micro‑architecture, and verification, helping to raise RTL quality and project predictability.

Key responsibilities

• Analyze flow results, identify root causes and relate them to RTL, constraints, tools and methodology.
• Define quality requirements, monitor regressions, violation trends and sign‑off status.
• Collaborate with RTL build, DFT, clock/reset, low‑power, physical‑design, verification and CAD teams to resolve technical issues.
• Assess new tool releases and methodology capabilities, coordinating their integration into project environments.
• Improve runtime, debug efficiency, waiver management, reporting and training through automation, reusable scripts and engineering guidelines.

Required profile

• Bachelor’s degree in Electrical Engineering, Computer Engineering or related field, or equivalent experience.
• 3+ years of experience in ASIC or SoC RTL design or design‑methodology.
• Hands‑on experience with Verilog or SystemVerilog build, analysis and debugging.
• Strong knowledge of digital design concepts such as pipelines, FSMs, clock/reset architectures, synchronizers, asynchronous FIFOs, metastability and power‑domain crossings.
• Experience with front‑end methodologies (lint, CDC/RDC, structural RTL analysis, low‑power verification, synthesis, timing constraints).
• Proficiency in Linux development environments and scripting (Python, Tcl, Perl, shell).

Required skills

• Verilog / SystemVerilog
• Python, Tcl, Perl, Shell scripting
• Linux development
• CDC, RDC, Lint, Structural RTL analysis
• Low‑power verification, UPF
• Synthesis, Timing constraints, SDC
• Static timing analysis, Formal verification, Equivalence checking
• Tools such as Meridian, SpyGlass, VC CDC, Questa CDC, Design Auditor, Power insertion