Staff DFT Engineer

About the role

Analog Devices is looking for a Staff DFT Engineer to own and drive the complete DFT strategy for complex SoCs, from architecture through production silicon. The role calls for deep hands-on expertise, strong technical judgment and the ability to lead and mentor junior engineers while working with design, physical design, validation and manufacturing teams. It is a senior, experienced position (7+ years of hands-on DFT experience) with about 10% travel required.

Key responsibilities

• DFT architecture and planning: define scan, compression, LBIST, MBIST, boundary scan and test access strategies, and drive testability requirements early in RTL design
• DFT implementation: lead scan insertion, stitching and DRC closure, ATPG (stuck-at, transition, path delay), test compression and pattern optimization, and DFT signoff
• ATPG and test quality: generate and optimize patterns, achieve high fault coverage with minimal pattern count, and diagnose coverage holes
• Silicon bring-up and production support: support first silicon, failure analysis and yield ramp, debug scan and BIST issues, and drive ECOs
• Technical leadership: act as DFT technical lead for one or more chips, guide junior and senior engineers, and define best practices and reusable methodologies
• Cross-functional collaboration with RTL designers, physical design, functional verification and product engineering

Required profile

• Bachelor's or Master's degree in Electrical/Electronics Engineering or a related field
• 7+ years of hands-on experience in DFT methodologies and industry-standard test techniques
• Proven experience leading DFT teams through end-to-end SoC execution, from architecture to silicon bring-up
• Nice to have: high-volume production test and ATE bring-up experience, exposure to automotive or industrial safety-critical applications, on-chip debug experience, and mentoring experience

Required skills

• Deep knowledge of logic BIST, ATPG, DFT rule checks, scan chain compression, memory BIST, boundary scan (IEEE 1149.1), JTAG and analog DFT
• Proficiency with DFT EDA tools such as Cadence and Siemens
• Scripting in Python, Tcl and/or Perl for DFT automation and log analysis
• Solid understanding of RTL design, Lint/CDC, low-power checks and the full ASIC design flow