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Staff Design Verification Engineer (Digital Design)

analogdevices · Rmz

New
Senior 🇬🇧 English
SystemVerilog UVM Verilog NoC Formal verification UPF SystemC Python TCL Gate-level simulation

Job description

About the role

Analog Devices is looking for a Digital Design Staff Verification Engineer to join its design verification team for highly integrated solutions and products. The role covers pre-silicon verification of SoC or subsystem designs, driving real revenue growth on next-generation edge products across several business units. It is a senior team position with about 10% travel required.

Key responsibilities

  • Lead pre-silicon verification of complex SoC or subsystem designs, from planning to closure
  • Verify microprocessor-based systems, AI/ML accelerators and high-speed peripherals
  • Architect and implement UVM-based testbenches, DV flows and scalable verification methodologies
  • Define and execute test plans, driving functional and code coverage closure with design teams
  • Work with emulation, FPGA and firmware teams to ensure end-to-end system correctness
  • Apply formal verification for IP and subsystem validation, and lead NoC/interconnect verification
  • Perform system-level use-case validation, including performance verification and analysis
  • Develop end-to-end scenarios and drive verification strategies that meet quality and schedule goals

Required profile

  • B.Tech/M.Tech with 8+ years of experience in digital pre-silicon verification
  • Proven verification closure using functional and code coverage at block and subsystem levels
  • Experience architecting testbench environments and implementing scalable DV flows
  • Hands-on power-aware verification with UPF, including power analysis and optimization
  • Strong communication and collaboration skills across global teams, and strong problem-solving ability

Required skills

  • Verilog/SystemVerilog and UVM-based testbench development and debugging
  • NoC, bus and interconnect verification, including coverage analysis
  • Formal verification, constrained-random verification, assertions and transaction-level modeling
  • Gate-level simulation with timing annotation
  • C/C++, SystemC and scripting (Python/TCL/Shell)
  • Processor-based systems (ARM, RISC-V, Tensilica), AI/ML or GPU architectures are a plus

Questions fréquentes

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Source : ats:workday

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Published 3 hours ago

Expires 1 month from now

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analogdevices

Rmz