SRAM Design Engineer

About the role

We are looking for a skilled SRAM Design Engineer to develop fast cache instances (FCI) for xPU (CPU/GPU) systems. You will work closely with CPU, GPU and APU teams to define specifications and deliver high‑performance memory blocks.

Key responsibilities

• Design and implement single‑port and dual‑port SRAM circuits for cache applications.
• Define design specifications in collaboration with CPU/GPU/APU teams.
• Optimize SRAM for power consumption, timing, area and yield.
• Perform schematic capture, simulations, margin checks and post‑layout analysis.
• Measure timing, power, leakage and drive post‑layout improvements.
• Collaborate with the layout team and validate designs (EM/IR, power‑on, lock‑up, etc.).
• Support post‑silicon debugging and validation efforts.

Required profile

• Experience designing SRAM for xPU or similar high‑performance computing systems.
• Ability to work with cross‑functional CPU/GPU/APU teams.
• Strong analytical skills for power, timing, area and yield optimization.
• Proficiency in schematic capture and simulation tools.

Required skills

• Python or Perl scripting.
• Verilog and SystemVerilog.
• XA, AFS‑Mega, HSPICE, NANOTIME, Virtuoso, Custom Compiler, XA‑RA, Totem.