Senior RTL Engineer – Silicon Design for AI/ML Hardware

About the role

You will help shape the future of AI/ML hardware acceleration by driving cutting‑edge TPU technology that powers Google’s most demanding AI/ML applications. The role focuses on designing and verifying complex digital RTL for custom silicon that accelerates machine‑learning workloads in data‑center accelerators.

Key responsibilities

• Own micro‑architecture and RTL implementation of complex IPs and subsystems, ensuring high quality and compliance with design methodology.
• Take responsibility for synthesis, timing/power closure, FPGA/silicon bring‑up, and drive PPA (Power, Performance, Area) improvements.
• Collaborate with architecture, verification, power, performance and physical design teams to deliver high‑quality designs for next‑generation data‑center accelerators.

Required profile

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science or related field, or equivalent practical experience.
• 8+ years of ASIC/SoC development experience using Verilog/SystemVerilog, including micro‑architecture, IP design, verification, synthesis, timing and power analysis, and DFT.
• Experience with programming languages such as Python, C/C++ or Perl and familiarity with SoC integration flows.

Required skills

• Verilog / SystemVerilog RTL coding.
• ASIC/SoC design and verification.
• Micro‑architecture and IP subsystem development.
• Synthesis, timing and power analysis, Design‑for‑Testing.
• Python, C++, Perl programming.
• Knowledge of arithmetic units, processor design, accelerators, bus architectures, NoC/fabric, and memory hierarchies.
• High‑performance and low‑power design techniques.